LM3S6422 Datasheet, PDF (9/609 Pages) Texas Instruments – Stellaris® LM3S6422 Microcontroller

Stellaris^® LM3S6422 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S6422 Microcontroller High-Level Block Diagram ............................... 37
Figure 2-1. CPU Block Diagram ............................................................................................. 46
Figure 2-2. TPIU Block Diagram ............................................................................................ 47
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 49
Figure 2-4. Bit-Band Mapping ................................................................................................ 69
Figure 2-5. Data Storage ....................................................................................................... 70
Figure 2-6. Vector Table ........................................................................................................ 76
Figure 2-7. Exception Stack Frame ........................................................................................ 78
Figure 3-1. SRD Use Example ............................................................................................... 92
Figure 4-1. JTAG Module Block Diagram .............................................................................. 151
Figure 4-2. Test Access Port State Machine ......................................................................... 155
Figure 4-3. IDCODE Register Format ................................................................................... 161
Figure 4-4. BYPASS Register Format ................................................................................... 161
Figure 4-5. Boundary Scan Register Format ......................................................................... 162
Figure 5-1. Basic RST Configuration .................................................................................... 165
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 166
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 166
Figure 5-4. Power Architecture ............................................................................................ 169
Figure 5-5. Main Clock Tree ................................................................................................ 171
Figure 6-1. Flash Block Diagram .......................................................................................... 225
Figure 7-1. GPIO Port Block Diagram ................................................................................... 256
Figure 7-2. GPIODATA Write Example ................................................................................. 257
Figure 7-3. GPIODATA Read Example ................................................................................. 257
Figure 8-1. GPTM Module Block Diagram ............................................................................ 298
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 302
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 303
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 304
Figure 9-1. WDT Module Block Diagram .............................................................................. 334
Figure 10-1. ADC Module Block Diagram ............................................................................... 358
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 362
Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 362
Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 363
Internal Temperature Sensor Characteristic ......................................................... 364
Figure 11-1. UART Module Block Diagram ............................................................................. 394
Figure 11-2. UART Character Frame ..................................................................................... 395
Figure 11-3. IrDA Data Modulation ......................................................................................... 397
Figure 12-1. SSI Module Block Diagram ................................................................................. 435
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 438
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 439
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 439
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 440
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 441
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 441
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 442
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 443
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 443
June 18, 2012
9
Texas Instruments-Production Data