LM3S6422 Datasheet, PDF (152/609 Pages) Texas Instruments – Stellaris® LM3S6422 Microcontroller

JTAG Interface
Table 4-2. JTAG_SWD_SWO Signals (108BGA)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SWCLK
A9
I
TTL
JTAG/SWD CLK.
SWDIO
B9
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
O
TTL
JTAG TDO and SWO.
TCK
A9
I
TTL
JTAG/SWD CLK.
TDI
B8
I
TTL
JTAG TDI.
TDO
A10
O
TTL
JTAG TDO and SWO.
TMS
B9
I/O
TTL
JTAG TMS and SWDIO.
TRST
A8
I
TTL
JTAG TRST.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
4.3 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 151. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 4-4 on page 159 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 565 for JTAG timing diagrams.
4.3.1
JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 4-3 on page 152. Detailed information on each pin
follows.
Table 4-3. JTAG Port Pins Reset State
Pin Name
TRST
TCK
TMS
TDI
TDO
Data Direction
Input
Input
Input
Input
Output
Internal Pull-Up Internal Pull-Down
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Drive Strength
N/A
N/A
N/A
N/A
2-mA driver
Drive Value
N/A
N/A
N/A
N/A
High-Z
152
June 18, 2012
Texas Instruments-Production Data