LM3S6422 Datasheet, PDF (24/609 Pages) Texas Instruments – Stellaris® LM3S6422 Microcontroller

Revision History
Table 1. Revision History (continued)
Date
April 2009
Revision Description
5367 ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 157).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 18-4 on page 561).
■ Additional minor data sheet clarifications and corrections.
January 2009
4660
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Added "Hardware Configuration" section to Ethernet Controller chapter.
■ Additional minor data sheet clarifications and corrections.
November 2008
4283
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
October 2008
4149
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ In the Ethernet chapter, major improvements were made including a rewrite of the conceptual
information and the addition of new figures to clarify how to use the Ethernet Controller interface.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
August 2008
3447
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
July 2008
3108
■ Corrected resistor value in ERBIAS signal description.
■ Additional minor data sheet clarifications and corrections.
May 2008
2972
■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
indicated as available and have now been changed to a No Connect (NC):
– Ball C1: Changed PE7 to NC
– Ball C2: Changed PE6 to NC
■ As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported:
TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit
fields in the MR23 register are now marked as reserved.
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS.
A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device
revisions (see “Functional Description” on page 476).
■ Additional minor data sheet clarifications and corrections.
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June 18, 2012
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