LM3S6422 Datasheet, PDF (256/609 Pages) Texas Instruments – Stellaris® LM3S6422 Microcontroller

General-Purpose Input/Outputs (GPIOs)
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
7-1 on page 256). The LM3S6422 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
Figure 7-1. GPIO Port Block Diagram
Commit
Control
GPIOLOCK
GPIOCR
Alternate Input
Alternate Output
Alternate Output Enable
Data
Control
GPIODATA
GPIODIR
Mode
Control
GPIOAFSEL
GPIO Input
GPIO Output
GPIO Output Enable
Pad Input
Pad Output
Pad Output Enable
Digital
I/O Pad
Package I/O Pin
Interrupt
Interrupt
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
7.2.1
7.2.1.1
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 264) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
256
June 18, 2012
Texas Instruments-Production Data