DRV3201-Q1_16 Datasheet, PDF (9/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

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DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
6.5 Electrical Characteristics
over operating temperature T_J = –40°C to 150°C and recommended operating conditions, VS = 4.75 to 30 V, f_PWM< 30 kHz
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
POWER SUPPLY
I_VSq
VS quiescent current shut down
VS = 14 V, no operation, T_J < 85°C EN = low, RSTN =
(sleep mode)
high⁽¹⁾ total leakage current on all supply connected pins
I_VSn
VS quiescent current normal operation See Figure 14 and Figure 15.
(boost converter enabled, drivers not
switching)
VCC5
Internal supply voltage
VS > 6 V, external load current < 100 µA. Decoupling
capacitance is typically 4.7 nF.
VCC3
Internal supply voltage
VS > 3 V, external load current < 100 µA. Decoupling
capacitance is typically 4.7 nF.
VS >4.75 V, external load current < 100µA. Decoupling
capacitance is typically 4.7 nF.
CURRENT SENSE AMPLIFIER FIRST STAGES
V_off1/2
V_{off1/2_d}
I_leak,INxIPx
Initial input offset of amplifiers at
T_J = 25°C
Temperature and aging offset
Input leakage current INx, IPx
0 V < INx, IPx < 1 V pin-to-pin and pin-to-ground
–0.3 V < INx, IPx < 0 V pin-to-pin and pin-to-ground
G_o1/2
V_{O1/2_N}
DC open loop gain
Nominal output voltage range
See Note ⁽³⁾
Normal voltage operation, VS ≥ 6 V, ADREF = 5 V; 0.5-
mA load current
V_{O1/2_L}
GBP_1/2
SR_1/2
PSRR_1/2
Output voltage range during low voltage Low voltage operation, 4.75 V ≤ VS ≤ 6 V, ADREF = 5
operation
V; 0.5-mA load current
Gain bandwidth product (GBP)
0.5 V ≤ O1/2 ≤ 4.5 V ⁽³⁾
Slew rate
0.5 V ≤ O1/2 ≤ 4.5 V, capacitor load = 25 pF
Power supply rejection ratio
VS to O1/2. Decoupling capacitance is typically 4.7 nF
on VCC5 and VCC3. ⁽³⁾
CMRR_1/2
Common mode rejection ratio
CURRENT SENSE AMPLIFIER SECOND STAGES
IN1/2 or IP1/2 to O1/2 ⁽³⁾
V_off3/4
V_{off3/4_d}
V_{O3/4_N}
Initial input offset of amplifiers at
T_J = 25 °C
Temperature and aging offset
Nominal output voltage range
VRO = 2.5 V
Normal voltage operation, VS ≥ 6 V, ADREF = 5 V; 0.5-
mA load current
V_{O3/4_L}
GBP_3/4
SR_3/4
G1
Output voltage range during low voltage Low voltage operation, 4.75 V ≤ VS ≤ 6 V, ADREF = 5
operation
V; 0.5-mA load current
Gain bandwidth product (GBP)
0.5 V ≤ O3/4 ≤ 4.5 V, gain = 8 ⁽³⁾
Slew rate
0.5 V ≤ O3/4 ≤ 4.5 V, capacitor load = 25 pF
Gain1
G2
Gain2
G3
Gain3
G4
Gain4
PSRR_3/4
Power supply rejection ratio
VS to O3/4 decoupling capacitance is typically 4.7 nF on
VCC5 and VCC3. ⁽³⁾
SHIFT BUFFER
VRI
Shift input voltage range
VRO
Shift output voltage range
VR_offset
I_RO
I_leak,RI
Shift voltage offset
Shift output current capability
Input leakage current RI
VRI = 2.5 V, pin-to-ground
MIN
4.7
2.1 ⁽²⁾
3.15
TYP MAX UNIT
30 _µA
40
20
mA
5.3 _V
3.6 _V
3.45 _V
–1
0
1 mV
–1
0
1 mV
–0.5
0.5 µA
–50
0.5 µA
80
dB
0.5
4.5 V
0.5
4V
5
MHz
2.9
15 V/µs
80
dB
80
dB
–5
0
5 mV
–3
0
3 mV
0.5
4.5 V
0.5
4V
5
MHz
2.9
15 V/µs
1.98
2 2.02 V/V
3.96
4 4.04 V/V
5.82
6 6.18 V/V
7.84
8 8.16 V/V
80
dB
0.1
2.6 V
0.1
2.6 V
–5
5 mV
–5
5 mA
–0.2
0.2 µA
(1) The DRV3201 can only enter Sleep Mode when EN is set to low while RSTN is kept high. Once the device is in Sleep Mode (100 µs
after EN has been set low), the RSTN pin can be set low without affecting the Sleep Mode.
(2) Lower limit of functional range dependent of internal PowerOnReset level for internal digital logic. It is specified by VS > 3 V the internal
digital logic is operational and not put into PowerOnReset.
(3) Specified by design
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