DRV3201-Q1_16 Datasheet, PDF (23/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

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DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
CSM
LOW
HIGH
ERR pin configuration
(CFG1)
Do not care
1
0
Table 2. Error Reporting in the Safety Modes
Description
All error conditions are flagged on ERR pin
ERR pin only shows errors for protective actions that are enabled in CSM
All error conditions are flagged on ERR pin
The ERR pin goes up again after a read out of the respective error flag in the status register once the respective
violation condition disappears. In case the MCU reads out the respective error flag in the status register while the
respective error condition is still present, the ERR pin shows a short positive pulse (pulse width typically 100 ns).
This behavior helps show the distinction between a loss of clock error and a VS undervoltage or overvoltage
error flag during self-tests of these safety features. After activation of these self-tests in configuration register 0
(CFG0) bit 6, the ERR pin goes down. After an MCU read out of the VS undervoltage/overvoltage flags in status
register 1 (STAT1) bits 1:0, the ERR pin should stay low if the loss of clock self-test is working properly. If the
ERR pin shows a positive pulse (pulse width typically 100 ns), this is an indication of a failure in the loss of clock
self-test.
7.3.5.3 Additional Safety Features
7.3.5.3.1 IHSx/ILSx Input Readback/Edge Counter
To verify the signal path to the DRV3201-Q1, the device allows reading back the logic level of all IHSx and ILSx
inputs from the RB0 address. These values directly reflect the state of the pin and are not registered. It is
required to ensure that the state of the IHSx and ILSx pins do not change while reading back their levels through
SPI.
IHSx/ILSx Input Readback remains operational even if PWM Mode is chosen. In this case the ILSx Readback
may be used to read any logic level signal.
The edge counter allows a more robust and less time critical verification of the ILSx/IHSx signal chain and may
be more convenient to use during normal operation. This counter can be used to count the number of edges on
one or more IHSx/ILSx inputs. The MCU selects the inputs to be observed and arms the counter by writing to the
SPI register RB1. When the start bit is removed the counter stops counting edges. The obtained counter value
can be read from the SPI register RB2 and it resets by setting the CLEAR bit in SPI register RB1.
When the counter has reached its maximum value of 255 it stops counting and remains in this state.
IHSx/ILSx edge counter remains operational even if PWM Mode is chosen, and in this case it may be used to
count edges at any connected input.
7.3.5.3.2 Gate-Source Voltage Monitoring
The DRV3201-Q1 provides a gate-source voltage monitoring feature for the external MOSFETs. For each
external MOSFET, the VGS is monitored by a comparator with 1 V as a lower threshold, and 9 V as a higher
threshold.
For each external MOSFET, a status flag is set in SPI status register 2 (STAT2), bits 0:5. Each status bit is set to
1 when the respective VGS rises greater than 9 V and they are set to 0 when the respective VGS drops below 1
V. This feature is intended for diagnostic use after start-up to turn on or turn off the external MOSFETs and
check the respective status bits.
7.3.5.4 Ultima Ratio Support
Under certain circumstances it may be required to turn on all FETs simultaneously, which is supported by this
device. However, to minimize risk of accidental triggering two requirements need to be satisfied:
1. The MCU is required to perform an unlock sequence of three different consecutive SPI transfers.
2. When the last SPI command is sent all IHSx and ILSx inputs need to be at a high level already.
This feature is only available when operating in direct mode.
Copyright © 2012–2015, Texas Instruments Incorporated
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