DRV3201-Q1_16 Datasheet, PDF (36/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
Bits R/W
7:6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
Reset
2’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
Table 16. Status Register 2 (STAT2)space(Addr. 0x12)
Definition
Reserved
HS2 VGS comparator (0 if VGS < 1 V, 1 if VGS > 9 V)
HS1 VGS comparator (0 if VGS < 1 V, 1 if VGS > 9 V)
HS0 VGS comparator (0 if VGS < 1 V, 1 if VGS > 9 V)
LS2 VGS comparator (0 if VGS < 1 V, 1 if VGS > 9 V)
LS1 VGS comparator (0 if VGS < 1 V, 1 if VGS > 9 V)
LS0 VGS comparator (0 if VGS < 1 V, 1 if VGS > 9 V)
Bits R/W
7:1
RO
0
RO
Table 17. CRC Control Register (CRCCTL)space(Addr. 0x20)
Reset
7’h0
1’h0
Definition
Reserved
Starts configuration data CRC8 calculation. Bit gets cleared when calculation is finished
To perform CRC check:
1.Calculate CRC checksum
2.Store calculated checksum in CRCEXP register
3.Set bit 0 CRC control register (CRCCTL) to 1
4.Bit gets cleared when calculation is finished
5.Failing checksum is indicated in STAT1 register
6.Calculated checksum can be read from CRCCALC register
Table 18. CRC Calculated Checksum Register (CRCCALC)space(Addr. 0x21)
Bits R/W
7:0
RO
Reset
8’h0
Definition
Checksum generated by internal CRC engine
Bits R/W
7:0
RW
Table 19. CRC Expected Checksum Register (CRCEXP)space(Addr. 0x22)
Reset
8’h0
Definition
Checksum externally calculated by microcontroller
Bits R/W
7
RO
6
RO
5
RO
4
RO
3
RO
2
RO
1
RO
0
RO
Reset
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
Table 20. Input Read Back (RB0)space(Addr. 0x23)
Definition
Reserved
CSM input
LS2 input
LS1 input
LS0 input
HS2 input
HS1 input
HS0 input
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