DRV3201-Q1_16 Datasheet, PDF (26/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
www.ti.com
7.3.7 Boost Converter
The boost converter is based on a burst mode fixed frequency controller. During the on-time, the internal low-
side boost FET is turned on until the current limit level is detected. The off-time is calculated proportionally from
an independent 2.5-MHz time-reference by sensing the supply voltage VS and the output voltage VBOOST. A
hysteretic comparator (low-level VBOOST-VS = 14 V, high level VBOOST-VS = 16 V) determines
starting/stopping the burst pulsing. The nominal switching frequency during the burst pulsing is 2.5 MHz.
The maximum current in the coil can be adjusted by the resistor Rboost_shunt such that the maximum coil
current is limited to 0.1 V/Rboost_shunt. This current limit is used by the controller to switch off the internal low-
side boost FET. TI recommends choosing a coil with a current saturation level of at least 30% above the current
limit level set with the resistor Rboost_shunt.
A second internal current limit is implemented that triggers at higher currents and acts as a second level of
protection for the internal low-side boost FET in case the resistor R1 is shorted. If the Rboost_shunt is shorted,
the second current limit is used by the controller to switch off the internal low-side boost FET. Because the
second internal current limit is higher than the normal current limit set by Rboost-shunt and only meant for
protecting the internal boost FET, the external coil may saturate if the second internal current limit becomes
active. To allow the external MCU to detect this possible failure condition, the second internal current limit sets
the boost undervoltage flag (register STAT1, bit 2). This causes a shutdown of the gate-drivers depending on the
configured safety mode.
To reduce noise level on the chip the boost converter can be switched off during sensitive current measurements
with the B_EN pin. As long as the disable time interval is short enough, the boost output capacitor can keep the
boost output voltage high enough. When the boost converter is disabled, the boost undervoltage monitor is active
to ensure the driver-stages are still operating correctly. During the boost undervoltage condition, the boost
switching frequency folds back to around half the normal operating frequency. This does not affect the current
limit.
7.3.8 Gate-Drivers
The DRV3201-Q1 has three high-side and low-side gate-drivers. Each high-side and low-side gate-driver
contains a programmable sourcing and sinking current to charge and discharge the gate of the external power
FETs.
The digital logic prevents the simultaneous activation of high and low-side gate-driver of one power-stage. If a
command from the MCU for simultaneous activation is detected, the failure is flagged in the status register.
7.3.8.1 Gate-Driver Slope Control
The DRV3201-Q1 has been designed to support adaptive slope control by programmable sink and source
currents to charge and discharge the gates of the external power FETs. Table 3 gives the slope registers which
are supported to program the sink and source currents of the gate-drivers.
Affected Gate-Drivers
HS1 and HS2
HS1 and HS2
LS1 and LS2
LS1 and LS2
HS3
HS3
LS3
LS3
Table 3. Slope Configuration Registers
Register
HS1/2 Slope Register (CURR0)
HS1/2 Slope Register (CURR0)
LS1/2 Slope Register (CURR1)
LS1/2 Slope Register (CURR1)
HS3 Slope Register (CURR2)
HS3 Slope Register (CURR2)
LS3 Slope Register (CURR3)
LS3 Slope Register (CURR3)
Slope
Rising Edge
Falling Edge
Rising Edge
Falling Edge
Rising Edge
Falling Edge
Rising Edge
Falling Edge
Current Range
140mA–1A
140mA–1A
140mA–1A
140mA–1A
140mA–1A
140mA–1A
140mA–1A
140mA–1A
Number of steps
8
8
8
8
8
8
8
8
26
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