DRV3201-Q1_16 Datasheet, PDF (22/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
www.ti.com
Feature Description (continued)
7.3.5.1.8 SPI Error
If the DRV3201-Q1 receives an invalid write or read access, the SPI OK bit in status register 1 (STAT1) is set to
0. This bit is set to 1 after a read out of this register by the MCU.
7.3.5.1.9 EEPROM CRC Check
After each wake up to active mode, the DRV3201-Q1 performs an EEPROM CRC check. If the calculated CRC8
checksum does not match the CRC8 checksum stored in the EEPROM, the EEPROM Data CRC Failed flag is
set in status register 1 (STAT1).
7.3.5.1.10 Configuration Data CRC Check
The DRV3201-Q1 offers a security feature to permanently ensure configuration integrity employing a CRC8
checksum mechanism. The MCU can start a CRC8 checksum calculation within the DRV3201-Q1 over all
configuration registers by setting bit 0 in the CRC control register (CRCCTL) to 1. This bit stays set until the CRC
calculation is finished. There may not be any write access while the CRC engine is running, otherwise the CRC8
checksum becomes corrupt. The CRC8 checksum value calculated by the DRV3201-Q1 is stored in the CRC
calculated checksum register (CRCCALC).
The MCU itself can also calculate the expected CRC8 checksum value, based on the vector given below, and
store this expected value in the CRC expected checksum register (CRCEXP). This should be done before the
MCU initiates the CRC8 checksum calculation within the DRV3201-Q1. After the DRV3201-Q1 does the CRC
calculation, if the expected CRC stored in the CRCEXP register does not match the calculated CRC in
CRCCALC register, the Configuration Data CRC Failed flag is set in status register 1 (STAT1).
The MCU may then read back all configuration registers to search for the bit error and perform corrective actions.
The CRC8 calculation mechanism is a generic one with following presets:
• The polynomial used is: (0 1 2 8)
• Initial value is: 11111111
See Table 1 for CRC data vector.
[47:40]
[39:32]
[31:28]
[27:22]
[21:16]
[15:10]
[ 9: 4]
[ 3: 0]
Table 1. CRC Data Vector
Bit Number
CRC8 Data Bus Values
CFG0
CFG1
CFG2
CURR0
CURR1
CURR2
CURR3
0000
7.3.5.1.11 Loss of Clock
If the internal clock gets stuck, the loss of clock monitor pulls the ERR pin low. During a test of this block the
ERR is also low. This self-check is combined with the VS comparator self-test (see VS Comparator Check).
7.3.5.2 Error Indication on ERR Pin
The ERR pin is an indicator for a detected error condition. It may act as interrupt to the external MCU, after
which the MCU reads all status registers to determine which error condition is detected. After entering active
mode this pin remains high as long as no error condition is detected, in case of a detected error condition the
ERR pin goes low. Error reporting occurs according to Table 2.
22
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DRV3201-Q1