DRV3201-Q1_16 Datasheet, PDF (16/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
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7.3 Feature Description
7.3.1 Supply Concept
The battery voltage functional operation range for the DRV3201-Q1 is from 4.85 V to 30 V. The DRV3201-Q1
operates with either 3.3 V or 5 V MCUs, which can be achieved by connecting the IO voltage of the MCU to the
VDD_IO pin of the DRV3201-Q1, and by connecting the ADC reference voltage of the MCU to the ADREF pin of
the DRV3201-Q1. All digital outputs are related to VDDIO, and all analog outputs are related (clamped) to
ADREF. All digital inputs are related to the internal supply VCC3, except the EN pin. The gate-drivers for the
external power FETs operate even during battery voltage drops down to 4.75 V when coming from full functional
battery voltage range. For supply voltage falling less than 4.75 V, the gates of the external FETs are pulled down
actively. For supply voltage less than 3 V, these gates are pulled down semi-actively. The minimum start-up
battery voltage for the gate-drivers and the internal logic is 4.85 V.
Coming from full functional battery voltage range (that is, from 4.85 V to 30 V) the internal logic, including the SPI
interface, operates even during battery voltage drops down to 3 V. When the battery drops less than 3 V, the
DRV3201-Q1 triggers a complete internal reset, clearing all internal status bits and registers. Also, the SPI
communication to the MCU is disabled when the DRV3201-Q1 logic is put in reset.
The VCC5 is an internal supply for the current sense amplifiers and other internal analog circuitry. The VCC5 pin
needs to be externally decoupled with a typical 4.7 nF-capacitance. The VCC5 has an internal current limit to
avoid any internal damage due to an external short-to-ground on the VCC5 pin.
The VCC3 is an internal supply for the internal logic. The VCC3 pin needs to be externally decoupled with a
typical 4.7-nF capacitance. Because the VCC3 is supplied from the VCC5 regulator, its output is current limited
by the VCC5 current limit so any internal damage is avoided in case of an external short-to-ground on the VCC3
pin. In case of a short-to-ground on either the VCC5 pin or the VCC3 pin, the internal logic is put in reset, which
is detectable by the MCU because of disabled SPI communication. In this situation it is strongly recommended
that the MCU takes necessary action to bring down the EN pin and shut off the DRV3201-Q1 to avoid VCC5
and/or VCC3 overloading for too long.
7.3.1.1 Boost Converter
The boost converter is configured to supply an add-on voltage to the supply voltage. The boost converter
requires an external inductance, capacitor, Schottky-diode, and a series resistance in its ground for current
sensing. Both the high-side and the low-side gate-drivers are supplied from the boost converter. This allows the
DRV3201-Q1 to achieve full-range gate-source driving voltage for all external power FETs even at battery
voltage down to 4.75 V. The boost converter has a separate B_EN pin to enable/disable. When the device is put
in sleep mode, the boost converter cannot be enabled.
7.3.2 Digital Input, Output Pins
All digital input pins (marked HVI_D in terminal function table), except the EN pin, have a threshold voltage
related to the internal VCC3 supply. Therefore, the state of these input pins is effective regardless of whether the
VDDIO level is out of limits. These digital input pins have a fail-safe ESD structure with only a reverse diode path
to ground, and no reverse diode path to any supply voltage. Depending on the function, these input pins have an
internal passive pulldown or pullup. All digital output pins (marked LVO_D) have a push-pull stage between
VDDIO and ground. Therefore, the logic high-levels are related to VDDIO.
7.3.3 Reset
The DRV3201-Q1 can be reset by switching the RSTN to low. When RSTN is low, all status bits and register
settings are cleared, the boost converter and the current sense amplifiers are off, and the gate-driver outputs are
actively pulled low with the maximum setting for the sink current, hence turning off the external power FETs. The
internal supplies VCC3 and VCC5 are still active when RSTN is forced low. The input high and low thresholds of
RSTN are related to VCC3, and therefore independent of VDDIO, hence the state of the RSTN pin is effective
regardless of whether the VDDIO level is out of limits. Once the RSTN pin has been set low, the device cannot
enter Sleep Mode.
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