DRV3201-Q1_16 Datasheet, PDF (29/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

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7.5 Programming
DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
7.5.1 SPI Interface
The SPI slave interface is used for serial communication with external SPI master (external MCU). The SPI
communication starts with the NCS falling edge, and ends with NCS rising edge. The NCS high level keeps SPI
slave interface in reset state, and SDO output 3-stated.
7.5.1.1 Address Mode Transfer
The address mode transfer is an 8-bit protocol. Both SPI slave and SPI master transmit the MSB first.
1
2
3
4
5
6
7
8
NCS
SCLK
SDI
R7
R6
R5
R4
R3
R2
R1
R0 X
SDO
D7
D6
D5
D4
D3
D2
D1
D0 X
NOTE: SPI Master (MCU) and SPI Slave (DRV3201) sample received data on the falling SCLK edge, and transmit on rising SCLK edge
B82442A1683K Inductor Used
Figure 11. Single 8-bit SPI Frame/Examples
After the NCS falling edge, the first word of 7 bits are address bits followed by the RW bit. During the first
address transfer, the device returns the STAT1 register on SDO. Each complete 8-bit frame is processed. The
bits are ignored if NCS goes high before a multiple of 8 bits is transferred.
7.5.1.2 SPI Address Transfer Phase
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
RW
FIELD NAME
ADDR [6:0]
RW
BIT DEFINITION
Register Address
RW = 1: Write access
RW = 0: Read access
When RW = 0, the SPI master performs a read access to the selected register. During the following SPI transfer,
the device returns the requested register read value on SDO, and interprets SDI bits as a next address transfer.
When RW = 1, the master performs a write access on the selected register. The slave updates the register value
during the next SPI transfer (if followed immediately) and returns the current register value on SDO.
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