DRV3201-Q1_16 Datasheet, PDF (27/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

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DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
To reduce the risk of a distorted slope due to changing the slope setting, a new slope setting for a rising edge
only becomes active after the next falling edge of the affected gate-driver and vice versa for the falling edge. This
does not apply directly after wake up to active mode. As long as no low-side or high-side gate-driver has been
switched after wake up to active mode, the programmed slope settings are active immediately.
To allow a high scalability of the output FETs and switching speed, there is also one general reduced current
mode setting, in which all gate charge/discharge currents are 25% of the programmed settings. Furthermore it is
possible to set the drivers to switching mode by setting bit 7 in configuration register 1 (CFG1) to 1. In this setting
the drivers are not current limited and limiting the switching speed can be done externally with resistors in the
gate lines. In this mode, TI strongly recommends setting the slope registers (CURR0–3) to 0x3F to get the
maximum current setting and have the current limiting only from the external resistors.
7.3.8.2 Semi-Active Pulldown Resistor
Each high and low-side driver has a typical 500-kΩ resistor from gate to source acting as passive pulldown to
keep the external power FET turned off in unsupplied conditions. In addition a semi-active pulldown circuit is
reducing the gate impedance at a typical voltage of 2 V to about 7 kΩ. This semi-active pulldown circuit is turned
off in normal operation to avoid higher DC current consumption for the gate-driver.
7.3.8.3 Gate-Driver Shutoff Paths
Table 4 summarizes the possible states of the EN, RSTN and DRVOFF pins and the effect on the gate-drivers.
Table 4. Gate-Driver Shutoff Paths
EN
0
1
1≥0
RSTN DRVOFF Any Non-Masked
Error
Gate-Driver Shutoff
Unpowered device⁽¹⁾
Semi-active pulldown + passive pulldown
Logic
X
X
X
Semi-active pulldown + passive pulldown Reset
0
X
X
Active pulldown
Reset
1
1
0
X
Active pulldown
1 ⁽¹⁾
Active pulldown
Enabled
Enabled
0
0
Active, controlled by inputs
Enabled
X
X
X
Active pulldown, afterwards device enters
sleep mode ≥ semi-active pulldown +
passive pulldown
Enabled during active pulldown, afterwards
reset in sleep mode
(1) For 3 V < VS < 4.75 V, the VS undervoltage detection actively pulls down the gates of the external FETs. For VS < 3 V, these gates are
pulled down semi-actively.
7.4 Device Functional Modes
7.4.1 Sleep Mode, Active Mode
The EN (Enable) pin puts the device into sleep mode, in which it consumes less than 35 µA. At the falling edge
on the EN pin, after a typical 6-µs deglitch time, the gates of the external power FETs are actively pulled low by
the gate-drivers. Afterwards (minimum 20 µs, maximum 35 µs later) the internal supplies VCC5, VCC3, the boost
converter, and the current sense amplifiers are switched off and the gates of the external power FETs are pulled
low with a semi-active pulldown resistor (see Semi-Active Pulldown Resistor). The internal logic is put in reset
state, and all internal registers are cleared. No diagnostic information is available during sleep mode. When
putting the device into Sleep Mode, the RSTN pin must be kept high. Once the device is in Sleep Mode (100 µs
after EN has been set low), the RSTN pin can be set low without affecting the Sleep Mode.
A rising edge on the EN pin puts the device in active mode after typically 3 ms power-up time. In active mode,
the supplies VCC5 and VCC3 are present, and the boost converter can be enabled or disabled with the B_EN
pin. Because all internal registers are cleared in sleep mode, the MCU must program the DRV3201-Q1 in the
desired settings after each wake up from sleep mode to active mode.
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