DRV3201-Q1_16 Datasheet, PDF (10/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
www.ti.com
Electrical Characteristics (continued)
over operating temperature T_J = –40°C to 150°C and recommended operating conditions, VS = 4.75 to 30 V, f_PWM< 30 kHz
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
ADREF
V_oxm
Maximum DC voltage of O1/2/3/4
relative to ADREF
ADREF = 3.3/ 5 V; Ox-ADREF
–0.25
0.03 0.25 V
V_oxos
Overshoot of O1/2/3/4 over ADREF
Ox-ADREF; for < 1 µs; never higher than 5 V over
GND ⁽³⁾
1.2 V
I_ADREF
Bias current for voltage clamping circuit ADREF = 3.3/5 V, pin-to-ground
GATE-DRIVER
150 µA
V_GS,low
Gate-source voltage low high/low-side
driver
Active pulldown, I_load = –2 mA
0
0.2 V
R_GSp
R_GSsa
R_GSa2
R_GSa1
R_GSa0
V_GS,HS,high
V_GS,LS,high
IGC2C
Passive gate-source resistance
Semi-active gate-source resistance
Active gate-source resistance
Active gate-source resistance
Active gate-source resistance
high-side output voltage
low-side output voltage
Gate charge current high/low-side
driver 2
V_gs ≤ 200 mV
In sleep mode, V_gs > 2 V
V_gs < 1 V, gate driven low by gate-driver, Regyx = 100
V_gs < 1 V, gate driven low by gate-driver, Regyx = 010
V_gs < 1 V, gate driven low by gate-driver, Regyx = 001
I_load = –2 mA
I_load = –2 mA
2 V ≤ (VGLSx-VSLSx) ≤ 5 V, Regyx = 100, if not
disabled in CFG1
80
500
700 kΩ
7
8 kΩ
2.3 Ω
4.5 Ω
9Ω
9
12.8 V
9
12.8 V
0.4
0.57 0.74 A
IGC1C
Gate charge current high/low-side
driver 1
2 V ≤ (VGLSx-VSLSx) ≤ 5 V , Regyx = 010, if not
disabled in CFG1
0.2
0.29 0.37 A
IGC0C
Gate charge current high/low-side
driver 0
2 V ≤ (VGLSx-VSLSx) ≤ 5 V, Regyx = 001, if not
disabled in CFG1
0.1
0.14 0.18 A
IGD2D
Gate discharge current high/low-side
driver 2
2 V ≤ (VGLSx-VSLSx) ≤ 5 V, Regyx = 100, if not
disabled in CFG1
0.4
0.57 0.74 A
IGD1D
Gate discharge current high/low-side
driver 1
2 V ≤ (VGLS-VSLS) ≤ 5 V, Regyx = 010, if not disabled
in CFG1
0.2
0.29 0.37 A
IGD0D
Gate discharge current high/low-side
driver 0
2 V ≤ (VGLS-VSLS) ≤ 5 V, Regyx = 001, if not disabled
in CFG1
0.1
0.14 0.18 A
A_dt
Accuracy of dead time
BOOST CONVERTER
If not disabled in CFG1
–15%
15%
I_BOOSTn
BOOST pin quiescent current normal
operation (drivers not switching)
4.75 V < VS < 32 V
4.75 V < VS < 32 V (>25°C)
20 mA
15 mA
I_BOOST,sw
BOOST pin additional load current due
to switching gate-drivers
Without external power FETS (pure internal switching
current, 30kHz all gate-drivers switching at the same
time)
3 mA
V_BOOST
I_BOOST
f_BOOST
V_BOOSTUV
V_{GNDLS_B,off}
Boost output voltage
BOOST-VS voltage
Output current capability
Switching frequency
Undervoltage shutdown Level
Including Iboostn
BOOST-VS > V_BOOSTUV ⁽⁴⁾
BOOST-VS voltage
Voltage at GNDLS_B pin at which boost
FET switches off due to current limit
13.8
15
16 V
40
mA
2
2.5
3 MHz
11
11.9 V
70
100
130 mV
I_SW,fail
Internal second level current limit
R_DS(on)
Resistance BOOST FET
DIGITAL INPUTS
420
700 mA
0.48
1.2 Ω
INL
Input low threshold
All digital inputs: RSTN, B_EN, NCS, DRVOFF, ILSx,
IHSx, CSM, SDI, SCLK
0.9 V
ENL
EN input low threshold
0.27 ×
VDDIO
V
INH
Input high threshold
All digital inputs: RSTN, B_EN, NCS, DRVOFF, ILSx,
IHSx, CSM, SDI, SCLK
2.3
V
ENH
EN input high threshold
0.65 × VDDIO
V
Inhys
Input hysteresis
All digital inputs: RSTN, B_EN, NCS, DRVOFF, ILSx,
IHSx, CSM, SDI, SCLK
0.3
0.8
1V
(4) During start-up when BOOST-VS < V_BOOSTUV , f_BOOST is typically 1.25 MHz.
10
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