DRV3201-Q1_16 Datasheet, PDF (17/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

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DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
Feature Description (continued)
7.3.4 Current Measurement
The two channel current measurement is measured by the voltage drop across two external shunt resistors. It
contains one shift buffer, two first and two second stages.
7.3.4.1 Shift Buffer
The DRV3201-Q1 offers a unity gain amplifier that is normally used to support a shift voltage with lower output
impedance. This allows each current sense path to handle negative common mode voltages across the external
shunt resistor. The shift voltage is applied externally on the RI pin, with the actual shift voltage buffered on the
RO pin.
The RI input pin is a high-impedance input to a MOS gate with internal ESD protection to ground. There is no
reverse pullup path present to any supply (fail-safe ESD structure).
7.3.4.2 Two First Stage Amplifiers
A first stage operational amplifier operates with an external resistor network for higher flexibility to adjust the
current measurement to the application requirements.
In the recommended application, a shift voltage that may be based on an external reference (for example, an
external voltage regulator) can be added to move the transfer curve. Each channel of the first amplifier has its
own output going to the input of the MCU ADC.
The input of the first stage is high voltage compatible, so the device can be used to measure the voltage drop
across the low-side MOSFET for low requirement applications. The maximum output voltage of the O1 and O2
pins is clamped to the ADREF voltage.
The input pins INx and IPx pin are high-impedance inputs to a MOS gate with internal ESD protection to ground.
There is no reverse pullup path present to any supply (fail-safe ESD structure).
7.3.4.3 Two Second Stage Amplifiers
The second stage amplifiers with a separately programmable gain enable a higher resolution measurement at
low current. They can be directly connected to inputs of the MCU ADC.
The gain of the second stage amplifiers is programmable by SPI in steps two, four, six and eight using the CFG2
register.
The maximum output voltage of the O3 and O4 pins is clamped to the ADREF voltage.
7.3.4.4 ADREF Voltage Clamp
The maximum output voltage of pins O1–O4 is clamped to the voltage applied to ADREF by an active clamp.
The ADREF voltage is the reference supply voltage for the ADC in the MCU, so the outputs O1–O4 have a
maximum signal range related to the input range of the ADC in the MCU. The active clamp consumes a
maximum of 100 µA from the ADREF pin.
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