DRV3201-Q1_16 Datasheet, PDF (12/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
6.6 Serial Peripheral Interface Timing
f_SPI
T_SPI
t_high
t_low
t_sMCUs
t_d1
t_susi
t_d2
t_hcs
t_hlcs
t_tri
SPI clock (SCLK) frequency
SPI clock period
High time: SCLK logic high duration
Low time: SCLK logic low duration
Setup time NCS: time between falling edge of NCS and rising edge of SCLK
Delay time: time delay from falling edge of NCS to data valid at SDO
Setup time at SDI: setup time of SDI before the rising edge of SCLK
Delay time: time delay from falling edge of SCLK to data valid at SDO
Hold time: time between the falling edge of SCLK and rising edge of NCS
SPI transfer inactive time: time between two transfers
3-state delay time: time between rising edge of NCS and SDO in 3-state
(1) MAX SPI clock tolerance is ± 10%.
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MIN NOM MAX UNIT
4⁽¹⁾ MHz
250
ns
90
ns
90
ns
90
ns
60 ns
30
ns
0
45 ns
45
ns
250
ns
15 ns
12
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