DRV3201-Q1_16 Datasheet, PDF (30/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
7.5.1.3 SPI Data Transfer Phase
Bit
Function
D7
DATA7
D6
DATA6
D5
DATA5
D4
DATA4
D3
DATA3
D2
DATA2
D1
DATA1
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D0
DATA0
FIELD NAME BIT DEFINITION
DATA [7:0]
Data value for write access (8-bit)
The table shows a data value encoding scheme during a write access. It is possible to mix the two access
modes (write and read access) during one SPI communication sequence (NCS = 0). The SPI communication can
be terminated after a single 8-bit SPI transfer by asserting NCS = 1. The device returns STAT1 register (for the
very first SPI transfer after power up) or current register value addressed during the SPI transfer address phase.
7.5.1.4 Device Data Response
Bit
Function
R7
REG7
R6
REG6
R5
REG5
R4
REG4
R3
REG3
R2
REG2
R1
REG1
R0
REG0
FIELD NAME BIT DEFINITION
REG [7:0]
Internal register value
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