DRV3201-Q1_16 Datasheet, PDF (33/60 Pages) Texas Instruments – DRV3201-Q1 3 Phase Motor Driver-IC for Automotive Safety Applications

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Bits
R/W
7
RW
6
RW
5
RW
4
RW
3
RW
2
RW
1
RW
0
RW
Bits R/W
7:4
RO
3:2
RW
1:0
RW
Bits R/W
7:6
RO
5:3
RW
2:0
RW
DRV3201-Q1
SLVSBD6D – MAY 2012 – REVISED AUGUST 2015
Table 8. Configuration Register 1 (CFG1)space(Addr. 0x02)
Reset
1’h0
1’h0
1’h1
1’h1
1’h1
1’h1
1’h1
1’h1
Definition
0: Adjustable HS/LS currents for rising/falling edges according to registers CURR0–3
1: Unlimited HS/LS currents for rising/falling edges
Set PWM mode
All gate-drivers can be driven with 3 PWM signals
ERR pin configuration
In CSM, ERR pin only shows errors that are actually handled in CSM if this bit is set or else all errors
are flagged
Enable LS VDS error handling in CSM
Enable HS VDS error handling in CSM
Enable programmable dead time in CSM
Enable boost undervoltage handling in CSM
Enable VS overvoltage handling in CSM
Table 9. Configuration Register 2 (CFG2)space(Addr. 0x03)
Reset
1’h0
2’h0
2’h0
Definition
Reserved
Current amplifier gain for second stage second amplifier (O4/O2)
00: 2
01: 4
10: 6
11: 8
Current amplifier gain for second stage first amplifier (O3/O1)
00: 2
01: 4
10: 6
11: 8
Reset
2’h0
3’h7
3’h7
Table 10. HS1/2 Slope Register (CURR0)space(Addr. 0x04)
Definition
Reserved
Adjust HS0/1 current for rising edge
000: 140 mA
001: 140 mA
010: 290 mA
011: 430 mA
100: 570 mA
101: 710 mA
110: 850 mA
111: 1 A
Adjust HS0/1current for falling edge
000: 140 mA
001: 140 mA
010: 290 mA
011: 430 mA
100: 570 mA
101: 710 mA
110: 850 mA
111: 1 A
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