LM3S2B93 Datasheet, PDF (809/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
16.3.2.1
Standard and Fast Modes
Standard and Fast modes are selected using a value in the I²C Master Timer Period (I2CMTPR)
register that results in an SCL frequency of 100 kbps for Standard mode.
The I²C clock rate is determined by the parameters CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2CMTPR register (see page 828).
The I²C clock period is calculated as follows:
SCL_PERIOD = 2 × (1 + TIMER_PRD) × (SCL_LP + SCL_HP) × CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/SCL_PERIOD = 333 Khz
Table 16-3 gives examples of the timer periods that should be used to generate SCL frequencies
based on various system clock frequencies.
Table 16-3. Examples of I²C Master Timer Period versus Speed Mode
System Clock
4 MHz
6 MHz
12.5 MHz
16.7 MHz
20 MHz
25 MHz
33 MHz
40 MHz
50 MHz
80 MHz
Timer Period
0x01
0x02
0x06
0x08
0x09
0x0C
0x10
0x13
0x18
0x27
Standard Mode
100 Kbps
100 Kbps
89 Kbps
93 Kbps
100 Kbps
96.2 Kbps
97.1 Kbps
100 Kbps
100 Kbps
100 Kbps
Timer Period
-
-
0x01
0x02
0x02
0x03
0x04
0x04
0x06
0x09
Fast Mode
-
-
312 Kbps
278 Kbps
333 Kbps
312 Kbps
330 Kbps
400 Kbps
357 Kbps
400 Kbps
16.3.3
Interrupts
The I²C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
January 20, 2012
809
Texas Instruments-Production Data