LM3S2B93 Datasheet, PDF (21/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
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Device Identification 1 (DID1), offset 0x004 ..................................................................... 237
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 239
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 240
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 242
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 244
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 247
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 249
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 251
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 252
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 256
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 259
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 261
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 262
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 265
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 268
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 270
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 274
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 278
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 282
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 284
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 286
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 288
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 290
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 293
Hibernation Module ..................................................................................................................... 295
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 306
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 307
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 308
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 309
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 310
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 313
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 315
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 317
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 319
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 320
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 321
Internal Memory ........................................................................................................................... 322
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 332
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 333
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 334
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 337
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 338
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 339
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 340
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 341
Register 9: Flash Control (FCTL), offset 0x0F8 ................................................................................. 342
Register 10: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 343
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 344
January 20, 2012
21
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