LM3S2B93 Datasheet, PDF (263/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
Bit/Field
23:21
20
19:18
17
16
15:12
11:10
9:8
Name
reserved
PWM
reserved
ADC1
ADC0
reserved
MAXADC1SPD
MAXADC0SPD
Type
RO
R/W
RO
R/W
R/W
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Clock Gating Control
This bit controls the clock gating for SAR ADC module 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Sample Speed
This field sets the rate at which ADC module 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
0
ADC0 Sample Speed
This field sets the rate at which ADC0 samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADC0SPD bit as follows (all other encodings are reserved):
Value Description
0x3 1M samples/second
0x2 500K samples/second
0x1 250K samples/second
0x0 125K samples/second
January 20, 2012
263
Texas Instruments-Production Data