LM3S2B93 Datasheet, PDF (544/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

External Peripheral Interface (EPI)
Register 32: EPI Error and Interrupt Status and Clear (EPIEISC), offset 0x21C
This register is used to clear a pending error interrupt. Clearing any defined bit in the EPIEISC has
no effect; setting a bit clears the error source and the raw error returns to 0. When any of these bits
are read as set it indicates that the ERRRIS bit in the EPIRIS register is set and an EPI controller
error is sent to the interrupt controller if the ERIM bit in the EPIIM register is set. If any of bits [2:0]
are written as 1, the register bit being written to, as well as the ERRIS bit in the EPIRIS register and
the ERIM bit in the EPIIM register are cleared. Note that writing to this register and reading back
immediately (pipelined by the processor) returns the old register contents. One cycle is needed
between write and read.
EPI Error and Interrupt Status and Clear (EPIEISC)
Base 0x400D.0000
Offset 0x21C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WTFULL RSTALL TOUT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
Name
reserved
WTFULL
RSTALL
Type
RO
R/W1C
R/W1C
Reset
0x000
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write FIFO Full Error
Value Description
0 The WFERR bit is not enabled or no writes are stalled.
1 The WFERR bit is enabled and a write is stalled due to the WFIFO
being full.
Writing a 1 to this bit clears it, as well as as the ERRRIS and ERIM bits.
Read Stalled Error
Value Description
0 The RSERR bit is not enabled or no pending reads are stalled.
1 The RSERR bit is enabled and a pending read is stalled due to
writes in the WFIFO.
Writing a 1 to this bit clears it, as well as as the ERRRIS and ERIM bits.
544
January 20, 2012
Texas Instruments-Production Data