LM3S2B93 Datasheet, PDF (738/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
5
4
3
2
Name
TXRIS
RXRIS
DSRRIS
DCDRIS
Type
RO
RO
RO
RO
Reset
0
0
0
0
Description
UART Transmit Raw Interrupt Status
Value Description
1 If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
0 No interrupt
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
UART Receive Raw Interrupt Status
Value Description
1 The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
0 No interrupt
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
UART Data Set Ready Modem Raw Interrupt Status
Value Description
1 Data Set Ready used for software flow control.
0 No interrupt
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
UART Data Carrier Detect Modem Raw Interrupt Status
Value Description
1 Data Carrier Detect used for software flow control.
0 No interrupt
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
738
January 20, 2012
Texas Instruments-Production Data