LM3S2B93 Datasheet, PDF (13/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 770
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 770
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 771
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 772
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 773
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 773
Figure 16-1. I²C Block Diagram ............................................................................................. 805
Figure 16-2. I²C Bus Configuration ........................................................................................ 806
Figure 16-3. START and STOP Conditions ............................................................................. 807
Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 807
Figure 16-5. R/S Bit in First Byte ............................................................................................ 808
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 808
Figure 16-7. Master Single TRANSMIT .................................................................................. 812
Figure 16-8. Master Single RECEIVE ..................................................................................... 813
Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 814
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 815
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 816
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 817
Figure 16-13. Slave Command Sequence ................................................................................ 818
Figure 17-1. I²S Block Diagram ............................................................................................. 843
Figure 17-2. I²S Data Transfer ............................................................................................... 846
Figure 17-3. Left-Justified Data Transfer ................................................................................ 846
Figure 17-4. Right-Justified Data Transfer .............................................................................. 846
Figure 18-1. CAN Controller Block Diagram ............................................................................ 880
Figure 18-2. CAN Data/Remote Frame .................................................................................. 882
Figure 18-3. Message Objects in a FIFO Buffer ...................................................................... 890
Figure 18-4. CAN Bit Time .................................................................................................... 894
Figure 19-1. Analog Comparator Module Block Diagram ......................................................... 931
Figure 19-2. Structure of Comparator Unit .............................................................................. 933
Figure 19-3. Comparator Internal Reference Structure ............................................................ 933
Figure 20-1. PWM Module Diagram ....................................................................................... 946
Figure 20-2. PWM Generator Block Diagram .......................................................................... 946
Figure 20-3. PWM Count-Down Mode .................................................................................... 951
Figure 20-4. PWM Count-Up/Down Mode .............................................................................. 951
Figure 20-5. PWM Generation Example In Count-Up/Down Mode ........................................... 952
Figure 20-6. PWM Dead-Band Generator ............................................................................... 952
Figure 21-1. QEI Block Diagram .......................................................................................... 1023
Figure 21-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1026
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1045
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1046
Figure 25-1. Load Conditions ............................................................................................... 1124
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1125
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1125
Figure 25-4. Power-On Reset Timing ................................................................................... 1126
Figure 25-5. Brown-Out Reset Timing .................................................................................. 1126
Figure 25-6. Power-On Reset and Voltage Parameters ......................................................... 1127
January 20, 2012
13
Texas Instruments-Production Data