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LM3S2B93 Datasheet, PDF (52/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller | |||
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Architectural Overview
â 8/16/32-bit dedicated parallel bus for external peripherals and memory
â Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory
â Blocking and non-blocking reads
â Separates processor from timing details through use of an internal write FIFO
â Efficient transfers using Micro Direct Memory Access Controller (µDMA)
â Separate channels for read and write
â Read channel request asserted by programmable levels on the internal non-blocking read
FIFO (NBRFIFO)
â Write channel request asserted by empty on the internal write FIFO (WFIFO)
The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.
â Synchronous Dynamic Random Access Memory (SDRAM) mode
â Supports x16 (single data rate) SDRAM at up to 50 MHz
â Supports low-cost SDRAMs up to 64 MB (512 megabits)
â Includes automatic refresh and access to all banks/rows
â Includes a Sleep/Standby mode to keep contents active with minimal power draw
â Multiplexed address/data interface for reduced pin count
â Host-Bus mode
â Traditional x8 and x16 MCU bus interface capabilities
â Similar device compatibility options as PIC, ATmega, 8051, and others
â Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)
â Support of both muxed and de-muxed address and data
â Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
â Speed controlled, with read and write data wait-state counters
â Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
â Manual chip-enable (or use extra address pins)
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January 20, 2012
Texas Instruments-Production Data
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