LM3S2B93 Datasheet, PDF (511/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
Bit/Field
23
22
21
20
19:16
15:8
Name
XFFEN
XFEEN
WRHIGH
RDHIGH
reserved
MAXWAIT
Type
R/W
R/W
R/W
R/W
RO
R/W
Reset
0
Description
External FIFO FULL Enable
Value Description
0 No effect.
1 An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL full signal is high, XFIFO writes
are stalled.
0
External FIFO EMPTY Enable
Value Description
0 No effect.
1 An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
0
0
0x0
0xFF
WRITE Strobe Polarity
Value Description
0 The WRITE strobe is WRn (active Low).
1 The WRITE strobe is WR (active High).
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the programmed write strobe polarity is used for
both CS0n and CS1n accesses.
READ Strobe Polarity
Value Description
0 The READ strobe is RDn (active Low).
1 The READ strobe is RD (active High).
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the programmed read strobe polarity is used for
both CS0n and CS1n accesses.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Maximum Wait
This field defines the maximum number of external clocks to wait while
an external FIFO ready signal is holding off a transaction (FFULL and
FEMPTY).
When the MAXWAIT value is reached the ERRRIS interrupt status bit
is set in the EPIRIS register. When this field is clear, the transaction can
be held off forever without a system interrupt.
Note:
When the MODE field is configured to be 0x2 and the BLKEN
bit is set in the EPICFG register, enabling HB8 mode, this
field defaults to 0xFF.
January 20, 2012
511
Texas Instruments-Production Data