LM3S2B93 Datasheet, PDF (625/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
Figure 13-4. Doubling the ADC Sample Rate
ADC Sample Clock
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GSYNC
ADC 0 PHASE 0x0 (0.0°)
ADC 1 PHASE 0x8 (180.0°)
Using the ADCSPC register, ADC0 and ADC1 may provide a number of interesting applications:
■ Coincident sampling of different signals. The sample sequence steps run coincidently in both
converters.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x0, sampling AIN1
■ Skewed sampling of the same signal. The sample sequence steps are 1/2 of an ADC clock (500
µs for a 1Ms/s ADC) out of phase with each other. This configuration doubles the conversion
bandwidth of a single input when software combines the results as shown in Figure
13-5 on page 625.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x8, sampling AIN0
Figure 13-5. Skewed Sampling
ADC0 S1 S2 S3 S4 S5 S6 S7 S8
ADC1
S1 S2 S3 S4 S5 S6 S7 S8
13.3.3
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
January 20, 2012
625
Texas Instruments-Production Data