LM3S2B93 Datasheet, PDF (1027/1194 Pages) Texas Instruments – Stellaris® LM3S2B93 Microcontroller

Stellaris^® LM3S2B93 Microcontroller
21.4
21.5
could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 2¹⁴. In this
case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute
accuracy were required, the microcontroller’s divide instruction could be used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt
status, interrupt status, and interrupt clear capabilities are provided.
Initialization and Configuration
The following example shows how to configure the Quadrature Encoder module to read back an
absolute position:
1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System
Control module (see page 270).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module (see page 282).
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. To determine which GPIOs to configure, see Table 23-4 on page 1070.
4. Configure the PMCn fields in the GPIOPCTL register to assign the QEI signals to the appropriate
pins (see page 459 and Table 23-5 on page 1078).
5. Configure the quadrature encoder to capture edges on both signals and maintain an absolute
position by resetting on index pulses. A 1000-line encoder with four edges per line, results in
4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) as the count
is zero-based.
■ Write the QEICTL register with the value of 0x0000.0018.
■ Write the QEIMAXPOS register with the value of 0x0000.0F9F.
6. Enable the quadrature encoder by setting bit 0 of the QEICTL register.
7. Delay until the encoder position is required.
8. Read the encoder position by reading the QEI Position (QEIPOS) register value.
Register Map
Table 21-3 on page 1028 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■ QEI0: 0x4002.C000
■ QEI1: 0x4002.D000
Note that the QEI module clock must be enabled before the registers can be programmed (see
page 270). There must be a delay of 3 system clocks after the QEI module clock is enabled before
any QEI module registers are accessed.
January 20, 2012
Texas Instruments-Production Data
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