DRV8320 Datasheet, PDF (68/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
11 Layout
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11.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
Bypass the DVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R
or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the
AGND pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SLx pins directly to PGND. Instead, use dedicated traces to connect
these pins to the sources of the low-side external MOSFETs. These recommendations allow for more accurate
V_DS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
11.1.1 Buck-Regulator Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI:
• Place the feedback network resistors close to the FB pin and away from the inductor to minimize coupling
noise into the feedback pin.
• Place the input bypass capacitor close to the VIN pin to reduce copper trace resistance which effects input
voltage ripple of the device.
• Place the inductor close to the SW pin to reduce magnetic and electrostatic noise.
• Place the output capacitor close to the junction of the inductor and the diode. The inductor, diode, and C_OUT
trace should be as short as possible to reduce conducted and radiated noise and increase overall efficiency.
• Make the ground connection for the diode, C_VIN, and C_OUT as small as possible and tie it to the system
ground plane in only one spot (preferably at the C_OUT ground point) to minimize conducted noise in the
system ground plane.
For more detail on switching power supply layout considerations refer to AN-1149 Layout Guidelines for
Switching Power Supplies (SNVA021).
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