DRV8320 Datasheet, PDF (28/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
www.ti.com
8.3 Feature Description
8.3.1 Three Phase Smart Gate Drivers
The DRV832x family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. A doubler charge pump provides the proper gate bias voltage to the high-
side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support. An
internal linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge gate drivers
can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV832x family of devices implement a smart gate-drive architecture which allows the user to dynamically
adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead-time
insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
8.3.1.1 PWM Control Modes
The DRV832x family of devices provides four different PWM control modes to support various commutation and
control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register
during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or
PWM_MODE change.
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 1.
Table 1. 6x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
0
L
L
Hi-Z
0
1
L
H
H
1
0
H
L
L
1
1
L
L
Hi-Z
8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 2.
Table 2. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
X
L
L
Hi-Z
1
0
H
H
L
1
1
L
L
H
8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV832x family of devices uses 6-step block commutation tables that are stored internally.
This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-
bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode normally
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin
low if this feature is not required.
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