DRV8320 Datasheet, PDF (47/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

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FAULT
V_SENSE
Overcurrent
(SEN_OCP)
Gate Driver
Fault
(GDF)
Thermal
Warning
(OTW)
Thermal
Shutdown
(OTSD)
CONDITION
Table 6. Fault Action and Response (continued)
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
OCP_MODE = 00b
nFAULT
Hi-Z
Active
V_SP > V_{SEN_OCP}
Gate voltage stuck > t_DRIVE
T_J > T_OTW
OCP_MODE = 01b
OCP_MODE = 10b
OCP_MODE = 11b or
DIS_SEN = 1b
DIS_GDF = 0b
DIS_GDF = 1b
OTW_REP = 1b
OTW_REP = 0b
nFAULT
nFAULT
None
nFAULT
None
nFAULT
None
Hi-Z
Active
Active
Hi-Z
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
T_J > T_OTSD
—
nFAULT
Hi-Z
Active
DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
RECOVERY
Latched:
CLR_FLT, ENABLE Pulse
Retry:
t_RETRY
No action
No action
Latched:
CLR_FLT, ENABLE Pulse
No action
Automatic:
T_J < T_OTW – T_HYS
No action
Automatic:
T_J < T_OTSD – T_HYS
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV832x family of devices. When the ENABLE pin is low, the device
enters a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled,
the charge pump is disabled, the DVDD regulator is disabled, and the SPI bus is disabled. The t_SLEEP time must
elapse after a falling edge on the ENABLE pin before the device enters sleep mode. The device comes out of
sleep mode automatically if the ENABLE pin is pulled high. The t_WAKE time must elapse before the device is
ready for inputs.
In sleep mode and when V_VM < V_UVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
8.4.1.2 Operating Mode
When the ENABLE pin is high and V_VM > V_UVLO, the device enters operating mode. The t_WAKE time must elapse
before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD regulator,
and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV832x family of devices enters a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (t_RST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the t_RST time window or else the device will begin the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
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Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R