DRV8320 Datasheet, PDF (4/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
www.ti.com
NAME
GLC
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
nFAULT
nSCS
PGND
SCLK
SDI
SDO
SHA
SHB
SHC
SLA
SLB
SLC
VCP
VDRAIN
VDS
VM
Pin Functions—32-Pin DRV8320 Devices (continued)
PIN
NO.
DRV8320H
DRV8320S
15
15
19
—
25
25
27
27
29
29
26
26
28
28
30
30
18
—
21
—
17
17
—
21
31
31
—
20
—
19
—
18
6
6
11
11
14
14
8
8
9
9
16
16
2
2
4
4
20
—
3
3
TYPE ⁽¹⁾
DESCRIPTION
O
I
I
I
I
I
I
I
I
NC
OD
I
PWR
I
I
OD
I
I
I
I
I
I
PWR
I
I
PWR
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Device power ground. Connect to system ground.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
High-side MOSFET drain sense input. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and
greater then or equal to 10-uF local capacitance between the VM and PGND pins.
DRV8320RH RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
DRV8320RS RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
PGND
1
CPL
2
CPH
3
VCP
4
VM
5
VDRAIN
6
GHA
7
SHA
8
GLA
9
SLA
10
Thermal
Pad
30
INHB
PGND
1
29
INLA
CPL
2
28
INHA
CPH
3
27
DVDD
VCP
4
26
AGND
VM
5
25
ENABLE
VDRAIN
6
24
NC
GHA
7
23
VDS
SHA
8
22
IDRIVE
GLA
9
21
MODE
SLA
10
Not to scale
Thermal
Pad
30
INHB
29
INLA
28
INHA
27
DVDD
26
AGND
25
ENABLE
24
nSCS
23
SCLK
22
SDI
21
SDO
Not to scale
4
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