DRV8320 Datasheet, PDF (48/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
www.ti.com
Device Functional Modes (continued)
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Continuous Conduction Mode (CCM)
The LMR16006 integrated buck regulator steps the input voltage down to a lower output voltage. In continuous
conduction mode (when the inductor current never reaches zero at CCM), the buck regulator operates in two
cycles. The power switch is connected between the VIN and SW pins. During the first cycle of operation, the
transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is
supplied by the C_OUT capacitor and the rising current through the inductor. During the second cycle of operation,
the transistor is open and the diode is forward biased because the inductor current cannot instantaneously
change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of
these two cycles determines the output voltage. Equation 7 and Equation 8 define the approximate output
voltage.
D ^VO
V_VIN
where
• D is the duty cycle of the switch
(7)
D' 1 D
(8)
The value of D and D' will be required for design calculations.
8.4.2.2 Eco-mode™ Control Scheme
The LMR16006 device operates with the Eco-mode control scheme at light load currents to improve efficiency by
reducing switching and gate-drive losses. The LMR16006 device is designed so that if the output voltage is
within regulation and the peak switch current at the end of any switching cycle is below the sleep-current
threshold, I_INDUCTOR ≤ 80 mA, the device enters Eco-mode. For Eco-mode operation, the LMR16006 device
senses peak current, not average or load current, so the load current when the device enters Eco-mode is
dependent on the input voltage, the output voltage, and the value of the output inductor. When the load current is
low and the output voltage is within regulation, the device enters Eco-mode and draws only 28-µA input
quiescent current.
8.5 Programming
This section applies only to the DRV832x SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV832x SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
• Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5 bit command data.
48
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