DRV8320 Datasheet, PDF (32/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
www.ti.com
8.3.1.3 Gate Driver Voltage Supplies
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM
voltage supply input. The charge pump allows the gate driver to properly bias the high-side MOSFET gate with
respect to the source across a wide input supply voltage range. The charge pump is regulated to maintain a fixed
output voltage of V_VM + 11 V and supports an average output current of 25 mA. When V_VM is less than 12 V, the
charge pump operates in full doubler mode and generates V_VCP = 2 × V_VM – 1.5 V when unloaded. The charge
pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions. The charge pump
requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VM and VCP pins to act as the storage
capacitor. Additionally, a X5R or X7R, 47-nF, VM-rated ceramic capacitor is required between the CPH and CPL
pins to act as the flying capacitor.
VM
VM
1 …F
VCP
CPH
47 nF
CPL
VM
Charge
Pump
Control
Figure 25. Charge Pump Architecture
The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The linear regulator allows the gate driver to properly bias the low-side MOSFET gate with respect to
ground. The linear regulator output is fixed at 11 V and supports an output current of 25 mA.
8.3.1.4 Smart Gate Drive Architecture
The DRV832x gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-
side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive
Control section. Figure 26 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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