DRV8320 Datasheet, PDF (16/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
7.6 SPI Timing Requirements⁽¹⁾
at T_A = –40°C to +125°C, V_VM = 6 to 60 V (unless otherwise noted)
SPI (nSCS, SCLK, SDI, SDO)
t_READY
t_CLK
t_CLKH
t_CLKL
t_{SU_SDI}
t_{H_SDI}
t_{D_SDO}
t_{SU_nSCS}
t_{H_nSCS}
t_{HI_nSCS}
t_{DIS_nSCS}
SPI ready after enable
VM > UVLO, ENABLE = 3.3 V
SCLK minimum period
SCLK minimum high time
SCLK minimum low time
SDI input data setup time
SDI input data hold time
SDO output data delay time
SCLK high to SDO valid
nSCS input setup time
nSCS input hold time
nSCS minimum high time before active low
nSCS disable time
nSCS high to SDO high impedance
(1) Specified by design and characterization data
tHI_nSCS tSU_nSCS
nSCS
SCLK
tCLK
tCLKH
tCLKL
www.ti.com
MIN NOM MAX UNIT
1 ms
100
ns
50
ns
50
ns
20
ns
30
ns
30 ns
50
ns
50
ns
400
ns
10
ns
tH_nSCS
SDI
X
MSB
tSU_SDI t_{H_SDI}
LSB
X
SDO
Z
MSB
tEN_nSCS tD_SDO
LSB
Figure 1. SPI Slave Mode Timing Diagram
Z
tDIS_nSCS
16
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R