DRV8320 Datasheet, PDF (50/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
8.6 Register Maps
This section applies only to the DRV832x SPI devices.
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NOTE
Do not modify reserved registers or addresses not listed in the register maps (Table 9). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
Name
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
Reserved
Reserved
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
CSA Control
Reserved
10
FAULT
SA_OC
Reserved
CBC
TRETRY
FAULT
SA_OC
Reserved
CBC
TRETRY
CSA_FET
9
8
VDS_OCP
GDF
SB_OC
SC_OC
DIS_CPUV
DIS_GDF
LOCK
TDRIVE
DEAD_TIME
VDS_OCP
GDF
SB_OC
SC_OC
DIS_CPUV
DIS_GDF
LOCK
TDRIVE
DEAD_TIME
VREF_DIV
LS_REF
Table 9. DRV8320S and DRV8320RS Register Map
7
6
5
4
DRV8320S and DRV8320RS
UVLO
OTSD
VDS_HA
VDS_LA
OTW
CPUV
VGS_HA
VGS_LA
OTW_REP
PWM_MODE
1PWM_COM
IDRIVEP_HS
IDRIVEP_LS
OCP_MODE
OCP_DEG
Reserved
Reserved
DRV8323S and DRV8323RS
UVLO
OTSD
VDS_HA
VDS_LA
OTW
CPUV
VGS_HA
VGS_LA
OTW_REP
PWM_MODE
1PWM_COM
IDRIVEP_HS
IDRIVEP_LS
OCP_MODE
OCP_DEG
CSA_GAIN
DIS_SEN
CSA_CAL_A
Reserved
3
VDS_HB
VGS_HB
1PWM_DIR
VDS_HB
VGS_HB
1PWM_DIR
CSA_CAL_B
2
1
VDS_LB
VDS_HC
VGS_LB
VGS_HC
COAST
BRAKE
IDRIVEN_HS
IDRIVEN_LS
VDS_LVL
0
VDS_LC
VGS_LC
CLR_FLT
VDS_LB
VDS_HC
VDS_LC
VGS_LB
VGS_HC
VGS_LC
COAST
BRAKE
CLR_FLT
IDRIVEN_HS
IDRIVEN_LS
VDS_LVL
CSA_CAL_C
SEN_LVL
Type
R
R
RW
RW
RW
RW
RW
RW
R
R
RW
RW
RW
RW
RW
RW
Address
0h
1h
2h
3h
4h
5h
6h
7h
0h
1h
2h
3h
4h
5h
6h
7h
50
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