DRV8320 Datasheet, PDF (39/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

www.ti.com
DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
To minimize DC offset and drift overtemperature, a DC calibration mode is provided and enabled through the SPI
registers (CSA_CAL_X) or through the CAL pin. When the calibration setting is enabled, the inputs to the
amplifier are shorted and the load is disconnected. DC calibration can occur at any time, even when the half-
bridges are operating. For the best results, perform DC calibration during the switching off period to reduce the
potential noise impact to the amplifier.
SO (V)
V_REF
V_LINEAR
V_VREF / 2
SP ± SN (V)
Figure 36. Bidirectional Current-Sense Output
SO
SO
VREF
V_VREF ± 0.25 V
V_{SO(range±)}
SP
AV
SN
I
R
SP ± SN
±0.3 V
±I × R
V_SO(off)max
V_OFF,
V_VREF / 2
V_DRIFT
0V
V_SO(off)min
V_SO(range+)
I×R
0.25 V
0.3 V
0V
Figure 37. Bidirectional Current Sense Regions
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
39
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R