DRV8320 Datasheet, PDF (34/80 Pages) Texas Instruments – 6 to 60-V Three-Phase Smart Gate Driver

DRV8320, DRV8320R
DRV8323, DRV8323R
SLVSDJ3 – FEBRUARY 2017
www.ti.com
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown I_STRONG current on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of V_GS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it begins to monitor the gate voltage of the external MOSFET. If
at the end of the t_DRIVE period the V_GS voltage has not reached the proper threshold the gate driver will report a
fault. To ensure that a false fault is not detected, a t_DRIVE time should be selected that is longer than the time
required to charge or discharge the MOSFET gate. The t_DRIVE time does not increase the PWM time and will
terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Register Maps section for SPI devices and in the Pin Diagrams section for hardware interface
devices.
Figure 27 shows an example of the TDRIVE state machine in operation.
V_INHx
V_INLx
V_GHx
I_GHx
I_HOLD
V_GLx
I_GLx
I_HOLD
I_DRIVE
tDEAD
IHOLD _ISTRONG
t_DRIVE
I_HOLD
tDEAD
I_STRONG ^IHOLD
I_DRIVE
t_DRIVE
tDEAD
I_STRONG IHOLD
I_DRIVE
tDEAD
IHOLD _ISTRONG
I_DRIVE
I_HOLD
t_DRIVE
t_DRIVE
Figure 27. TDRIVE State Machine
I_HOLD
I_HOLD
8.3.1.4.3 Propagation Delay
The propagation delay time (t_pd) is measured as the time between an input logic edge to a detected output
change. This time comprises three parts consisting of the digital input deglitcher delay, the digital propagation
delay, and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
8.3.1.4.4 MOSFET V_DS Monitors
The gate drivers implement adjustable V_DS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the V_DS trip point (V_{VDS_OCP}) for
longer than the deglitch time (t_OCP), an overcurrent condition is detected and action is taken according to the
device V_DS fault mode.
34
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DRV8320 DRV8320R DRV8323 DRV8323R