LM3S611-IQN50-C2T Datasheet, PDF (6/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
10.2 Signal Description ....................................................................................................... 330
10.3 Functional Description ................................................................................................. 330
10.3.1 Sample Sequencers .................................................................................................... 331
10.3.2 Module Control ............................................................................................................ 331
10.3.3 Hardware Sample Averaging Circuit ............................................................................. 332
10.3.4 Analog-to-Digital Converter .......................................................................................... 332
10.3.5 Differential Sampling ................................................................................................... 332
10.3.6 Test Modes ................................................................................................................. 335
10.3.7 Internal Temperature Sensor ........................................................................................ 335
10.4 Initialization and Configuration ..................................................................................... 336
10.4.1 Module Initialization ..................................................................................................... 336
10.4.2 Sample Sequencer Configuration ................................................................................. 336
10.5 Register Map .............................................................................................................. 337
10.6 Register Descriptions .................................................................................................. 338
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11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
11.6
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 366
Block Diagram ............................................................................................................ 367
Signal Description ....................................................................................................... 367
Functional Description ................................................................................................. 368
Transmit/Receive Logic ............................................................................................... 368
Baud-Rate Generation ................................................................................................. 368
Data Transmission ...................................................................................................... 369
FIFO Operation ........................................................................................................... 369
Interrupts .................................................................................................................... 370
Loopback Operation .................................................................................................... 371
Initialization and Configuration ..................................................................................... 371
Register Map .............................................................................................................. 372
Register Descriptions .................................................................................................. 373
12 Synchronous Serial Interface (SSI) .................................................................... 406
12.1 Block Diagram ............................................................................................................ 406
12.2 Signal Description ....................................................................................................... 406
12.3 Functional Description ................................................................................................. 407
12.3.1 Bit Rate Generation ..................................................................................................... 407
12.3.2 FIFO Operation ........................................................................................................... 407
12.3.3 Interrupts .................................................................................................................... 408
12.3.4 Frame Formats ........................................................................................................... 408
12.4 Initialization and Configuration ..................................................................................... 416
12.5 Register Map .............................................................................................................. 417
12.6 Register Descriptions .................................................................................................. 418
13 Inter-Integrated Circuit (I²C) Interface ................................................................ 444
13.1 Block Diagram ............................................................................................................ 445
13.2 Signal Description ....................................................................................................... 445
13.3 Functional Description ................................................................................................. 445
13.3.1 I²C Bus Functional Overview ........................................................................................ 446
13.3.2 Available Speed Modes ............................................................................................... 448
13.3.3 Interrupts .................................................................................................................... 449
13.3.4 Loopback Operation .................................................................................................... 449
13.3.5 Command Sequence Flow Charts ................................................................................ 449
13.4 Initialization and Configuration ..................................................................................... 457
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June 18, 2012
Texas Instruments-Production Data