LM3S611-IQN50-C2T Datasheet, PDF (229/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S611 Microcontroller
7.1 Block Diagram
Figure 7-1. GPIO Module Block Diagram
PA0
U0Rx
UART0
PA1
U0Tx
PA2
SSIClk
PA3
SSIFss
SSI
PA4
SSIRx
PA5
SSITx
PWM2
PWM4
PWM5
PE0
PE1
PB0
PWM2
PWM1
PB1
PWM3
PB2
I2CSCL
I²C
PB3
I2CSDA
PB4
PB5
PB6
PB7
JTAG
Fault
PWM0
PWM0
PWM1
PD0
PD1
UART1
U1Rx
U1Tx
PD2
PD3
CCP1 Timer 0 CCP0
PD4
PD5
PD6
PD7
CCP3 Timer 1 CCP2
CCP5 Timer 2 CCP4
GPIO Port C
7.2 Signal Description
GPIO signals have alternate hardware functions. Table 7-3 on page 231 lists the GPIO pins and their
analog and digital alternate functions. The AINx analog signals are not 5-V tolerant and go through
an isolation circuit before reaching their circuitry. These signals are configured by clearing the
corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding
AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. The digital alternate hardware
June 18, 2012
229
Texas Instruments-Production Data