LM3S611-IQN50-C2T Datasheet, PDF (200/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

System Control
NRND: Not recommended for new designs.
Bit/Field
12
11:5
4
3:2
1
0
Name
I2C0
reserved
SSI0
reserved
UART1
UART0
Type
R/W
RO
R/W
RO
R/W
R/W
Reset
0
0
0
0
0
0
Description
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
200
June 18, 2012
Texas Instruments-Production Data