LM3S611-IQN50-C2T Datasheet, PDF (10/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 415
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 416
Figure 13-1. I²C Block Diagram ............................................................................................. 445
Figure 13-2. I²C Bus Configuration ........................................................................................ 446
Figure 13-3. START and STOP Conditions ............................................................................. 446
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 447
Figure 13-5. R/S Bit in First Byte ............................................................................................ 447
Figure 13-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 447
Figure 13-7. Master Single SEND .......................................................................................... 451
Figure 13-8. Master Single RECEIVE ..................................................................................... 452
Figure 13-9. Master Burst SEND ........................................................................................... 453
Figure 13-10. Master Burst RECEIVE ...................................................................................... 454
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 455
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 456
Figure 13-13. Slave Command Sequence ................................................................................ 457
Figure 14-1. PWM Unit Diagram ............................................................................................ 482
Figure 14-2. PWM Module Block Diagram .............................................................................. 483
Figure 14-3. PWM Count-Down Mode .................................................................................... 484
Figure 14-4. PWM Count-Up/Down Mode .............................................................................. 485
Figure 14-5. PWM Generation Example In Count-Up/Down Mode ........................................... 485
Figure 14-6. PWM Dead-Band Generator ............................................................................... 486
Figure 15-1. 48-Pin QFP Package Pin Diagram ...................................................................... 520
Figure 18-1. Load Conditions ................................................................................................ 533
Figure 18-2. JTAG Test Clock Input Timing ............................................................................. 534
Figure 18-3. JTAG Test Access Port (TAP) Timing .................................................................. 535
Figure 18-4. JTAG TRST Timing ............................................................................................ 535
Figure 18-5. External Reset Timing (RST) .............................................................................. 536
Figure 18-6. Power-On Reset Timing ..................................................................................... 536
Figure 18-7. Brown-Out Reset Timing .................................................................................... 536
Figure 18-8. Software Reset Timing ....................................................................................... 537
Figure 18-9. Watchdog Reset Timing ..................................................................................... 537
Figure 18-10. LDO Reset Timing ............................................................................................. 537
Figure 18-11. ADC Input Equivalency Diagram ......................................................................... 539
Figure 18-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 540
Figure 18-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 540
Figure 18-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 541
Figure 18-15. I²C Timing ......................................................................................................... 542
Figure D-1. Stellaris LM3S611 48-Pin LQFP Package ............................................................ 569
Figure D-2. 48-Pin LQFP Tray Dimensions ........................................................................... 571
Figure D-3. 48-Pin LQFP Tape and Reel Dimensions ............................................................. 573
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June 18, 2012
Texas Instruments-Production Data