LM3S611-IQN50-C2T Datasheet, PDF (235/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S611 Microcontroller
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable.
7.3.5
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
7.4 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode
(GPIODIR=0 and GPIOAFSEL=0). Table 7-4 on page 235 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 7-5 on page 235 shows
how a rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 7-4. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Output (PWM)
1
X
0
1
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
X
?
?
?
?
?
PDR
?
?
X
X
?
?
?
?
?
DR2R
X
?
?
?
X
?
?
?
?
DR4R
X
?
?
?
X
?
?
?
?
DR8R
X
?
?
?
X
?
?
?
?
SLR
X
?
?
?
X
?
?
?
?
Table 7-5. GPIO Interrupt Configuration Example
Desired
Pin 2 Bit Value^a
Register
Interrupt
Event
7
6
5
4
Trigger
GPIOIS
0=edge
X
X
X
X
1=level
GPIOIBE
0=single
X
X
X
X
edge
1=both
edges
3
X
X
2
0
0
1
X
X
0
X
X
June 18, 2012
235
Texas Instruments-Production Data