LM3S611-IQN50-C2T Datasheet, PDF (19/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S611 Microcontroller
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PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 502
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 505
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 505
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 505
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 506
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 506
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 506
PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 507
PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 507
PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 507
PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 508
PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 508
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 508
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 509
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 509
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 509
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 510
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 510
PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 510
PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 511
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 511
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 511
PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 514
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 514
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 514
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 517
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 517
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 517
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 518
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 518
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 518
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 519
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 519
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 519
June 18, 2012
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