LM3S611-IQN50-C2T Datasheet, PDF (13/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S611 Microcontroller
List of Registers
The Cortex-M3 Processor ............................................................................................................. 43
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 50
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 50
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 50
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 50
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 50
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 50
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 50
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 50
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 50
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 50
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 50
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 50
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 50
Register 14: Stack Pointer (SP) ........................................................................................................... 51
Register 15: Link Register (LR) ............................................................................................................ 52
Register 16: Program Counter (PC) ..................................................................................................... 53
Register 17: Program Status Register (PSR) ........................................................................................ 54
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 58
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 59
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 60
Register 21: Control Register (CONTROL) ........................................................................................... 61
Cortex-M3 Peripherals ................................................................................................................... 85
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ............................................. 95
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 ................................................ 97
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ............................................. 98
Register 4: Interrupt 0-29 Set Enable (EN0), offset 0x100 .................................................................... 99
Register 5: Interrupt 0-29 Clear Enable (DIS0), offset 0x180 .............................................................. 100
Register 6: Interrupt 0-29 Set Pending (PEND0), offset 0x200 ........................................................... 101
Register 7: Interrupt 0-29 Clear Pending (UNPEND0), offset 0x280 ................................................... 102
Register 8: Interrupt 0-29 Active Bit (ACTIVE0), offset 0x300 ............................................................. 103
Register 9: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 104
Register 10: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 104
Register 11: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 104
Register 12: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 104
Register 13: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 104
Register 14: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 104
Register 15: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 104
Register 16: Interrupt 28-29 Priority (PRI7), offset 0x41C .................................................................... 104
Register 17: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 106
Register 18: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 107
Register 19: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 108
Register 20: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 111
Register 21: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 112
Register 22: System Control (SYSCTRL), offset 0xD10 ....................................................................... 114
June 18, 2012
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