LM3S611-IQN50-C2T Datasheet, PDF (18/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 429
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 430
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 431
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 432
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 433
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 434
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 435
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 436
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 437
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 438
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 439
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 440
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 441
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 442
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 443
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 444
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 460
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 461
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 465
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 466
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 467
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 468
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 469
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 470
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 471
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 473
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 474
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 476
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 477
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 478
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 479
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 480
Pulse Width Modulator (PWM) .................................................................................................... 481
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 491
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 492
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 493
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 494
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 495
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 496
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 497
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 498
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 499
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 500
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 500
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 500
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 502
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 502
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June 18, 2012
Texas Instruments-Production Data