LM3S611-IQN50-C2T Datasheet, PDF (16/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 286
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 289
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 291
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 292
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 293
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 295
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 296
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 297
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 298
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 299
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 300
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 301
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 302
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 303
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 304
Watchdog Timer ........................................................................................................................... 305
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 309
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 310
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 311
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 312
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 313
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 314
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 315
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 316
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 317
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 318
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 319
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 320
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 321
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 322
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 323
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 324
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 325
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 326
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 327
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 328
Analog-to-Digital Converter (ADC) ............................................................................................. 329
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 339
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 340
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 341
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 342
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 343
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 344
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 348
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 349
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 351
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 352
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 353
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June 18, 2012
Texas Instruments-Production Data