LM3S611-IQN50-C2T Datasheet, PDF (164/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

System Control
NRND: Not recommended for new designs.
Table 5-5. System Control Register Map (continued)
Offset Name
Type
Reset
Description
0x110
0x114
0x118
0x120
0x124
0x128
0x144
0x150
0x160
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
CLKVCLR
LDOARST
R/W
0x00000040 Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Sleep Mode Clock Gating Control Register 2
R/W
0x00000040 Deep Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 2
R/W
0x0780.0000 Deep Sleep Clock Configuration
R/W
0x0000.0000 Clock Verification Clear
R/W
0x0000.0000 Allow Unregulated LDO to Reset the Part
5.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
193
199
204
195
201
206
178
179
180
164
June 18, 2012
Texas Instruments-Production Data