LM3S611-IQN50-C2T Datasheet, PDF (213/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S611 Microcontroller
6.2.2.3
6.2.2.4
Table 6-1. Flash Protection Policy Combinations (continued)
FMPPEn
1
0
1
FMPREn
0
1
1
Protection
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register.
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 222) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 221).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 223).
Flash Memory Protection by Disabling Debug Access
Flash memory may also be protected by permanently disabling access to the Debug Access Port
(DAP) through the JTAG and SWD interfaces. Access is disabled by clearing the DBG field of the
FMPRE register.
If the DBG field in the Flash Memory Protection Read Enable (FMPRE) register is programmed
to 0x2, access to the DAP is enabled through the JTAG and SWD interfaces. If clear, access to the
DAP is disabled. The DBG field programming becomes permanent and irreversible after a commit
sequence is performed.
In the initial state provided from the factory, access is enabled in order to facilitate code development
and debug. Access to the DAP may be disabled at the end of the manufacturing flow, once all tests
have passed and software has been loaded. This change does not take effect until the next power-up
June 18, 2012
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