LM3S611-IQN50-C2T Datasheet, PDF (522/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

Signal Tables
NRND: Not recommended for new designs.
Table 16-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PA3
I/O
TTL
GPIO port A bit 3.
20
SSIFss
I/O
TTL
SSI frame.
PA4
I/O
TTL
GPIO port A bit 4.
21
SSIRx
I
TTL
SSI receive.
PA5
I/O
TTL
GPIO port A bit 5.
22
SSITx
O
TTL
SSI transmit.
23
VDD
-
Power Positive supply for I/O and some logic.
24
GND
-
Power Ground reference for logic and I/O pins.
PD0
I/O
TTL
GPIO port D bit 0.
25
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PD1
I/O
TTL
GPIO port D bit 1.
26
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PD2
I/O
TTL
GPIO port D bit 2.
27
U1Rx
I
TTL
UART module 1 receive.
PD3
I/O
TTL
GPIO port D bit 3.
28
U1Tx
O
TTL
UART module 1 transmit.
PB0
I/O
TTL
GPIO port B bit 0.
29
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PB1
I/O
TTL
GPIO port B bit 1.
30
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
31
GND
-
Power Ground reference for logic and I/O pins.
32
VDD
-
Power Positive supply for I/O and some logic.
PB2
I/O
TTL
GPIO port B bit 2.
33
I2CSCL
I/O
OD
I²C clock.
PB3
I/O
TTL
GPIO port B bit 3.
34
I2CSDA
I/O
OD
I²C data.
PE0
I/O
TTL
GPIO port E bit 0.
35
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PE1
I/O
TTL
GPIO port E bit 1.
36
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PC3
I/O
TTL
GPIO port C bit 3.
37
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
PC2
I/O
TTL
GPIO port C bit 2.
38
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
39
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
PC0
I/O
TTL
GPIO port C bit 0.
40
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
522
June 18, 2012
Texas Instruments-Production Data