LM3S611-IQN50-C2T Datasheet, PDF (232/574 Pages) Texas Instruments – Stellaris® LM3S611 Microcontroller

NRND: Not recommended for new designs.
General-Purpose Input/Outputs (GPIOs)
Table 7-3. GPIO Signals (48QFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PE1
36
I/O
TTL
GPIO port E bit 1.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
7.3 Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception
of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). A Power-On-Reset (POR) or asserting an external reset
(RST) puts both groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a Low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
7-2 on page 232). The LM3S611 microcontroller contains five ports and thus five of these physical
GPIO blocks.
Figure 7-2. GPIO Port Block Diagram
Mode
Control
GPIOAFSEL
Alternate Input
Alternate Output
Alternate Output Enable
Data
Control
GPIODATA
GPIODIR
GPIO Input
GPIO Output
GPIO Output Enable
Pad Input
Pad Output
Pad Output Enable
Digital
I/O Pad
Package I/O Pin
Interrupt
Interrupt
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
232
June 18, 2012
Texas Instruments-Production Data